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3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 256 x 256
FEATURES:
* * * * * * * * *
IDT72V8985
* *
256 x 256 channel non-blocking switch Automatic signal identification (ST-BUS(R), GCI) 8 RX inputs--32 channels at 64 Kbit/s per serial line 8 TX outputs--32 channels at 64 Kbit/s per serial line Three-state serial outputs Microprocessor Interface (8-bit data bus) Frame Integrity for data applications 3.3V Power Supply Available in 44-pin Plastic Leaded Chip Carrier (PLCC), 48-pin Small Shrink Outline Package (SSOP), and 44-pin Plastic Quad Flatpack (PQFP) Operating Temperature Range -40C to +85C 3.3V I/O with 5V Tolerant Inputs
and write access to individual channels. As an important function of a digital switch is to maintain sequence integrity and minimize throughput delay, the IDT72V8985 is an ideal solution for most switching needs.
FUNCTIONAL DESCRIPTION
Frame sequence, constant throughput delay, and guaranteed minimum delay are high priority requirements in today's integrated data and multimedia networks. The IDT72V8985 provides these functions on a per-channel basis using a standard microprocessor control interface. Each of the eight serial lines is designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data. In Processor Mode, the microprocessor can access the input and output time slots to control other devices such as ISDN transceivers and trunk interfaces. Supporting both GCI and ST-BUS(R) formats, IDT72V8985 has incorporated an internal circuit to automatically identify the polarity and format of the frame synchronization. A functional block diagram of the IDT72V8985 device is shown on page 1. The serial streams operate continuously at 2.048 Mb/s and are arranged in 125s wide frames each containing 32, 8-bit channels. Eight input (RX0-7) and eight output (TX0-7) serial streams are provided in the IDT72V8985 device allowing a complete 256 x 256 channel non-blocking switch matrix to be constructed. The serial interface clock for the device is 4.096 MHz.
DESCRIPTION:
The IDT72V8985 is a ST-BUS(R)/GCI compatible digital switch controlled by a microprocessor. The IDT72V8985 can handle as many as 256, 64 Kbit/s input and output channels. Those 256 channels are divided into 8 serial inputs and outputs, each of which consists of 32 channels. The IDT72V8985 provides perchannel variable or constant throughput delay modes and microprocessor read
FUNCTIONAL BLOCK DIAGRAM
C4i
F0i
VCC
GND
RESET(1)
ODE
RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7
Timing Unit
TX0
Output MUX
Transmit Serial Data Streams
TX1 TX2
Receive Serial Data Streams
Data Memory Control Register Connection Memory
TX3 TX4 TX5 TX6 TX7
Microprocessor Interface
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DS CS R/W A0/ DTA D0/ A5 D7
NOTE: 1. The RESET Input is only provided on the SSOP package.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp.
CCO
AUGUST 2003
DSC-5707/5
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
PIN CONFIGURATION
DNC(1)
DNC(1)
DNC(1)
TX1
36
INDEX
6
5
4
3
2
44
43
42
41
40
44
43
42
41
40
39
38
37
35
TX2
INDEX
DTA CCO
RX3 RX4 RX5 RX6 RX7 VCC F0i C4i A0 A1 A2
1
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
TX3 TX4 TX5 TX6 TX7 GND D0 D1 D2 D3 D4
RX3 RX4 RX5 RX6 RX7 VCC F0i C4i A0 A1 A2
34
DNC(1)
CCO
ODE
ODE TX0
DTA
RX2
RX1
RX0
TX0
TX1
TX2
RX1
RX2
RX0
1 2 3 4 5 6 7 8 9 10 11
33 32 31 30 29 28 27 26 25 24 23
TX3 TX4 TX5 TX6 TX7 GND D0 D1 D2 D3 D4
20
21
22
23
24
12
13
14
15
16
17
18
19
20
21
25
26
18
19
27
28
22
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D7
D6
D5
A3
A4
A5
DNC(1)
DS
R/W CS
(1)
A3
A4
A5
CS D7
D6
DNC(1)
D5
PLCC: 0.05in. pitch, 0.65in. x 0.65in (J44-1, order code: J) TOP VIEW
PQFP: 0.80mm pitch, 10mm x 10mm (DB44-1, order code: DB) TOP VIEW
GND DTA RX0 RX1 RX2 DNC(1) RX3 RX4 RX5 RX6 RX7 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
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CCO ODE TX0 TX1 TX2 DNC(1) TX3 TX4 TX5 TX6 TX7 GND VCC D0 D1 D2 D3 D4 DNC(1) D5 D6 D7 CS GND
RESET(2)
F0i C4i A0 A1 A2 DNC(1) A3 A4 A5 DS R/W
2 4
TOP VIEW
Package Type SSOP: 0.025in. pitch, 0.625in. x 0.295in.
NOTES: 1. DNC - Do Not Connect 2. The RESET Input is only provided on the SSOP package.
Reference Identifier SO48-1
Order Code PV
2
DNC(1)
DNC
DS R/W
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IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
PIN DESCRIPTIONS
SYMBOL
GND VCC
NAME
Ground. VCC Data Acknowledgment (Open Drain) RX Input 0 to 7 Frame Pulse Clock Address 0 to 5 Data Strobe Read/Write Chip Select Data Bus 0 to 7 TX Outputs 0 to 7 (Three-state Outputs) Output Drive Enable Control Channel Output Device Reset (Schmitt Trigger Input)
I/O
DESCRIPTION
Ground Rail. +3.3 Volt Power Supply. This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this output. Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s. This input accepts and automatically identifies frame synchronization signals formatted according to different backplane specifications such as ST-BUS(R) and GCI. 4.096 MHz serial clock for shifting data in and out of the data streams. These lines provide the address to IDT72V8985 internal registers. This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. Active LOW input enabling a microprocessor read or write of control register or internal memories. These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH, Connection Memory LOW and data memory. Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s. This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. If this is HIGH, each channel may still be put into high-impedance by software control. This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the contents of the CCO bit in the Connection Memory HIGH locations. This input (active LOW) puts the IDT72V8985 in its reset state that clears the device internal counters, registers and brings TX0-7 and microport data outputs to a high-impedance state. The time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET pin must be held LOW for a minimum of 100ns to reset the device.
DTA
RX0-7
O I I I I I I I I/O O I O I
F0i C4i
A0-A5 DS R/W
CS
D0-D7 TX0-7 ODE CCO
RESET
3
IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
FUNCTIONAL DESCRIPTION (Cont'd)
The received serial data is internally converted to parallel by the on chip serial-to-parallel converters and stored sequentially in a 256-position Data Memory. By using an internal counter that is reset by the input 8 KHz frame pulse, F0i, the incoming serial data streams can be framed and sequentially addressed. Depending on the type of information to be switched, the IDT72V8985 device can be programmed to perform time slot interchange functions with different throughput delay capabilities on a per-channel basis. The Variable Delay mode, most commonly used for voice applications, can be selected ensuring minimum throughput delay between input and output data. In Constant Delay mode, used in multiple or grouped channel data applications, the integrity of the information through the switch is maintained. CONNECTION MEMORY Data to be output on the serial streams may come from two sources: Data Memory or Connection Memory. The Connection Memory is split into HIGH and LOW parts and is associated with particular TX output streams. In Processor Mode, data output on the TX streams is taken from the Connection Memory Low and originates from the microprocessor (Figure 2). Where as in Connection Mode (Figure 1), data is read from Data Memory and originated from the incoming RX streams. Data destined for a particular channel on the serial output stream is read internally during the previous channel time slot to allow time for memory access and internal parallel-to-serial conversion. CONNECTION MODE In Connection Mode, the addresses of input source for all output channels are stored in the Connection Memory Low. The Connection Memory Low locations are mapped to corresponding 8-bit x 32-channel output. The contents of the Data Memory at the selected address are then transferred to the parallelto-serial converters before being output. By having the output channel to specify the input channel through the Connection Memory, input channels can be broadcast to several output channels. PROCESSOR MODE In Processor Mode the CPU writes data to the Connection Memory Low locations which correspond to the output link and channel number. The contents of the Connection Memory Low are transferred to the parallel-to-serial converter one channel before it is to be output and are transmitted each frame to the output until it is changed by the CPU. CONTROL The Connection Memory High bits (Table 4) control the per-channel functions available in the IDT72V8985. Output channels are selected into specific modes such as: Processor Mode or Connection mode, Variable or Constant throughput delay modes, Output Drivers Enabled or in three-state condition. There is also one bit to control the state of the CCO output pin.
OUTPUT DRIVE ENABLE (ODE) The ODE pin is the master output three-state control pin. If the ODE input is held LOW all TDM (Time Division Multiplexed) outputs will be placed in high impedance regardless Connection Memory High programming. However, if ODE is HIGH, the contents of Connection Memory High control the output state on a per-channel basis. SERIAL INTERFACE TIMING The IDT72V8985 master clock (C4i) is 4.096 MHz signal allowing serial data link configuration at 2.048 Mb/s to be implemented. The IDT72V8985 can automatically detect the presence of an input frame pulse, identify the type of backplane present on the serial interface, and format the synchronization pulse according to ST-BUS(R) or GCI interface specifications (active HIGH in GCI or active LOW in ST-BUS(R)). Upon determining the correct interface Connected to the serial port, the internal timing unit establishes the appropriate serial data bit transmit and sampling edges. In ST-BUS(R) mode, every second falling edge of the 4.096 MHz clock marks a boundary and the input data is clocked in by the rising edge, three quarters of the way into the bit cell. In GCI mode every second rising edge of the 4.096 MHz clock marks the bit boundary while data sampling is performed during the falling edge, at three quarters of the bit boundaries.
DELAY THROUGH THE IDT72V8985
The transfer of information from the input serial streams to the output serial streams results in a delay through the device. The delay through the IDT72V8985 device varies according to the mode selected in the V/C bit of the Connection Memory High. VARIABLE DELAY MODE The delay in Variable Delay Mode is dependent only on the combination of source and destination on the input and output streams. The minimum delay achievable in the IDT72V8985 device is three time slots. In the IDT72V8985 device, the information that is to be output in the same channel position as the information is input (position n), relative to frame pulse, will be output in the following frame (channel n, frame n+1). The same occurs if the input channels succeeding (n+1, n+2) the channel position as the information is input. The information switched to the third time slot after the input has entered the device (for instance, input channel 0 to output channel 3 or input channel 30 to output channel 1), is always output three channels later. Any switching configuration that provides three or more time slots between input and output channels, will have a throughput delay equal to the difference between the output and input channels; i.e., the throughput delay will be less than one frame. Table 1 shows the possible delays for the IDT72V8985 device in Variable Delay Mode. An example is shown in Figure 3. CONSTANT DELAY MODE In this mode frame integrity is maintained in all switching configurations by
RX
Receive Serial Data Streams
Data Memory Connection Memory
Transmit Serial Data Streams
TX
Receive Serial Data Streams
Data Memory Connection Memory
Transmit Serial Data Streams
TX
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Microprocessor
Figure 1. Connection Mode
4
Figure 2. Processor Mode
IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
making use of a multiple Data Memory buffer technique where input channels written in any of the buffers during frame N will be read out during frame N+2. In the IDT72V8985, the minimum throughput delay achievable in Constant Delay mode will be 32 time slots; for example, when input time slot 32 (channel 31) is switched to output time slot 1 (channel 0). Likewise, the maximum delay is achieved when the first time slot in a frame (channel 0) is switched to the last time slot in the frame (channel 31), resulting in 94 time slots of delay (see Figure 4). To summarize, any input time slot from input frame N will be always switched to the destination time slot on output frame N+2. In Constant Delay mode the device throughput delay is calculated according to the following formula: DELAY=[32+(32-IN)+(OUT-1)] IN =the number of the input time slot (from 1 to 32) OUT = the number of the output time slot (from 1 to 32).
MICROPROCESSOR PORT
The IDT72V8985 microprocessor port is a non-multiplexed bus architecture. The parallel port consists of an 8-bit parallel data bus (D0-D7), six address input lines (A0-A5) and four control lines (CS, DS, R/W and DTA). This parallel microport allows the access to the Control Registers, Connection Memory Low, Connection Memory High, and the Data Memory. All locations are read/written except for the Data Memory, which can be read only. Accesses from the microport to the Connection Memory and the Data Memory are multiplexed with accesses from the input and output TDM ports. This can cause variable Data Acknowledge delays (DTA). In the IDT72V8985 device, the DTA output provides a maximum acknowledgment delay of 800ns for read/write operations in the Connection Memory. However, for operations in the Data Memory (Processor Mode), the maximum acknowledgment delay can be 1220ns.
The Processor Enable bit (bit 6) places every output channel on every output stream in Processor Mode; i.e., the contents of the Connection Memory LOW (CML, see Table 5) are output on the output streams once every frame unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8985 behaves as if bits 2 (Channel Source) and 0 (Output Enable) of every Connection Memory High (CMH, see Table 4) locations were set to HIGH, regardless of the actual value. If PE is LOW, then bit 2 and 0 of each Connection Memory High location operates normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of the CML define the source information (stream and channel) of the time slot that is to be switched to an output. If the ODE input pin is LOW, then all the serial outputs are high-impedance. If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH) or disables (if LOW) for that particular channel. The contents of bit 1 (CCO) of each Connection Memory High Location (see Table 4) is output on CCO pin once every frame. The CCO pin is a 2.048 Mb/ s output, which carries 256 bits. If CCO bit is set HIGH, the corresponding bit on CCO output is transmitted HIGH. If CCO is LOW, the corresponding bit on the CCO output is transmitted LOW. The contents of the 256 CCO bits of the CMH are transmitted sequentially on to the CCO output pin and are synchronous to the TX streams. To allow for delay in any external control circuitry the contents of the CCO bit is output one channel before the corresponding channel on the TX streams. For example, the contents of CCO bit in position 0 (corresponding to TX0, CH0), is transmitted synchronously with the TX channel 31, bit 7. Bit 1's of CMH for channel 1 of streams 0-7 are output synchronously with TX channel 0 bits 7-0. INITIALIZATION During the microprocessor initialization routine, the microprocessor should program the desired active paths through the matrices, and put all other channels into the high impedance state. Care should be taken that no two Connected TX outputs drive the bus simultaneously. With the CMH setup, the microprocessor controlling the matrices can bring the ODE signal high to relinquish high impedance state control to the Connection Memory High bits outputs. The reset pin is designed to be used with board reset circuitry. During reset the TX serial streams will be put into high-impedance and the state of internal registers and counters will be reset. As the connection memory can be in any state after a power up, the ODE pin should be used to hold the TX streams in high-impedance until the per-channel output enable control in the connection memory high is appropriately programmed. The main difference between ODE and reset is, reset alters the state of the registers and counters where as ODE controls only the high-impedance state of the TX streams. RESET input is only provided on the SSOP packages.
SOFTWARE CONTROL
If the A5, A1, A0 address line inputs are LOW then the IDT72V8985 Internal Control Register is addressed (see Table 2). If A5 input line is high, then the remaining address input lines are used to select the 32 possible channels per input or output stream. As explained in the Control Register description, the address input lines and the Stream Address bits (STA) of the Control register give the user the capability of selecting all positions of IDT72V8985 Data and Connect memories. See Figure 5 for accessing internal memories. The data in the control register consists of Memory Select and Stream Address bits, Split Memory and Processor Enable bits (Table 3). In Split Memory mode (Bit 7 of the Control register) reads are from the Data Memory and writes are to the Connection Memory LOW. The Memory Select bits allow the Connection Memory High or LOW or the Data Memory to be chosen, and the Stream Address bits define internal memory subsections corresponding to input or output streams.
TABLE 2 ADDRESS MAPPING
A5 0 1 1 1 1 1 1 1 1
5
A4 X 0 0
* * * * *
A3 X 0 0
* * * * *
A2 X 0 0
* * * * *
A1 0 0 0
* * * * *
A0 0 0 1
* * * * *
LOCATION Control Register Channel 0 Channel 1
* * * * *
TABLE 1 VARIABLE DELAY MODE
Input Channel n n n Output Channel m=n, n+1 or n+2 m>n+2 m1
1
1
1
1
Channel 31
IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
Incoming Now
Time Slot 32 31 30 29 28............ 3 ABCDEF GH 21 I J
Outgoing Next
32 31........7 1 6 5 4 32
Outgoing Now
32 31.........7 6 5 4 J 3 2 1 Time Slot
JJJ
GHI
32 Slots
For J: DELAY=3 Slots, 32 Slots, 33 Slots, and 34 Slots For G, H, and I: DELAY= 3 slots
32 Slots
32 Slots
Figure 3. Variable Delay Mode
Incoming
Time Slot 32 31 30 29 28............ 3 ABCD EFGH 21 I J
Switching
J I H
Outgoing
32 31 30 29 28............. 3 2 1 Time Slot GFE DCBA
32 Slots
32 Slots
32 Slots
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For Slot 1 ("A"): IN=32, OUT=1, DELAY=(32-32)+32+(1-1)=32 time slots minimum delay For Slot 32 ("J"): IN=1, OUT=32, DELAY=(32-1)+32+(32-1)=94 time slots maximum delay
Figure 4. Constant Delay Mode
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IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
CRb7 CRb6 CRb5 CRb4 CRb3 CRb2 CRb1 CRb0
Control Register
The Control Register is only accessed when A5=0. All other address bits have no effect when A5=0. When A5 =1, only 32 bytes are randomly accessable via A0-A4 at any one instant. Which 32 bytes are accessed is determined by the state of CRb0 -CRb4. The 32 bytes correlate to 32 channel of one ST-BUS stream.
CRb4 0 1 1
CRb3 1 0 1
Connection Memory High
Connection Memory Low
Data Memory Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 31 Channel 31 Channel 31 Channel 31 Channel 31 Channel 31 Channel 31 Channel 31
CRb2 0 0 0 0 1 1 1 1
CRb1 0 0 1 1 0 0 1 1
CRb0 Stream 0 0 1 1 2 0 1 3 0 4 1 5 0 6 7 1
100000
100001
100010
111111
External Address Bits
A5-A0
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Figure 5. Addressing Internal Memories
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IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
TABLE 3 CONTROL REGISTER
7 SM 6 PE 5 X 4 MS1 3 MS0 2 STA2 1 STA1 0 STA0
Bit
7 6 5 4-3
Name
SM (Split Memory) PE (Processor Mode)
Description
When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory, except when the Control Register is accessed again. The Memory Select bits need to specify the memory for the operations. When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when in highimpedance. When 0, the Connection Memory bits for each channel determine what is output. unused 0-0 - Not to be used. 0-1 - Data Memory (read only from the CPU) 1-0 - Connection Memory LOW 1-1 - Connection Memory is HIGH The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the subsection of memory made accessible for subsequent operations.
MS1-MS0 (Memory Select Bits)
2-0
STA2-0 (Stream Address Bits)
x = don't care
TABLE 4 CONNECTION MEMORY HIGH
7 X 6 V/C 5 X 4 X 3 X 2 CS 1 CCO 0 OE
Bit
7,5,4,3 6 2
Name
unused
Description
V/C (Variable/Constant This bit is used to select between Variable (LOW) and Constant Delay (HIGH) modes on a per-channel basis. Throughput Delay Mode) CS (Channel Source) CCO (CCO Bit) OE (Output Enable) When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the Data Memory and determine the source of the connection to the location's channel and stream. This bit drives a bit time on the CCO output pin. This bit enables the output drivers on a per-channel basis. This allows individual channels on individual streams to be made high-impedance, allowing switch matrices to be constructed. A HIGH enables the driver and a LOW disables it.
1 0
x = don't care
TABLE 5 CONNECTION MEMORY LOW
7 SAB2 6 SAB1 5 SAB0 4 CAB4 3 CAB3 2 CAB2 1 CAB1 0 CAB0
Bit
7-5
Name
SAB2-0(1) (Source Stream Address Bits)
Description
These three bits are used to select eight source streams for the Connection.
4-0(1) CAB2-0(1) These five bits are used to select 32 different source channels for the Connection (the stream where the channel (Source Channel Address Bits) is present is defined by bits SAB2-0). Bit 4 is the most significant bit.
NOTE: 1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source of the Connection which is output on the channel and stream associated with this location.
8
IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Vcc Vi VO IO TS PD Parameter Symbol Voltage Voltage on Digital Inputs Voltage on Digital Outputs Current at Digital Outputs Storage Temperature Package Power Dissapation -55 Min. -0.3 GND - 0.3 GND - 0.3 Max. 5.0 VCC +0.5 VCC +0.3 20 +125 1 Unit V V V mA C W
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI TOP Parameter Positive Supply Input Voltage Operating Temperature Commercial Min. 3.0 0 -40 Typ.(1) 3.3 25 Max. 3.6 5.25 +85 Unit V V C
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only a functional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
NOTE: 1. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
DC ELECTRICAL CHARACTERISTICS
Symbol ICC VIH VIL IIL CI VOH IOH VOL IOL IOZ CO Parameter Supply Current Input High Voltage Input Low Voltage Input Leakage (Inputs) Input Capacitance Output High Voltage Output High Current Output Low Voltage Output Low Current High Impedance Leakage Output Pin Capacitance Min. 2.0 2.4 10 5 Typ.(1) 3 Max. 5 0.8 15 10 0.4 5 10 Units mA V V A pF V mA V mA A pF IOH = 10mA Sourcing. VOH = 0.8V IOL = 5mA Sinking. VOL = 0.4V VO between GND and VCC VI between GND and VCC Test Conditions Outputs Unloaded
NOTE: 1. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Test Point
VCC
Output Pin S1 CL GND
RL S2 GND
S1 is open circuit except when testing output levels or high impedance states. S2 is switched to VCC or GND when testing output levels or high impedance states.
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Figure 6. Output Load
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IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS(1) ST-BUS(R) TIMING
Symbol tF0iW tF0iS tF0iH tDAA tSTiS tSTiH tC4i tCL tCH tr, tf Parameter Frame Pulse Width Frame Pulse Setup Time Frame Pulse Hold Time TX delay Active to Active RX Setup Time RX Hold Time Clock Period CK Input Low CK Input High Clock Rise/Fall Time Min. 5 5 10 10 Typ.(2) 244 20 20 40 244 122 122 Max. 190 190 60 10 Units ns ns ns ns ns ns ns ns ns ns CL = 150pF Test Conditions
NOTE: 1. Timing is over recommended temperature and power supply voltages. 2. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
tF0iW F0i tF0iS C4i tDAA tf tCH tF0iH tC4i tCL
tr
Ch. 0, Bit 6 Ch. 0, Bit 5 Ch. 0, Bit 5 Ch. 0, Bit 6
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TX
Ch. 31, Bit 0
Ch. 0, Bit 7
tSTiS RX
Ch. 31, Bit 0 Ch. 0, Bit 7
tSTiH
Figure 7. ST-BUS(R) Timing
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IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS(1) GCI TIMING
Symbol tC4i tCL, tCH tWFH tF0iS tF0iH tDAA tSTiS tSTiH tr, tf Parameter Clock Period Pulse Width Frame Width High Frame Setup Frame Hold Data Delay/Clock Active to Active RX Input Setup RX Input Hold Clock Rise/Fall Time Min. 5 5 10 10 Typ.(2) 244 122 244 20 20 40 Max. 190 190 60 10 Units ns ns ns ns ns ns ns ns ns CL = 150pF Test Conditions
NOTE: 1. Timing is over recommended temperature and power supply voltages. 2. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
tWFH
F0i tF0iS tr tf tCL tF0iH tCH tC4i C4i
TX
Ch. 31
Bit 7 tDAA
Ch. 0
Bit 0
Ch. 0
Bit 1
tSTiS RX Ch. 31 Bit 7 Ch. 0
tSTiH Bit 0 Ch. 0 Bit 1
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Figure 8. GCI Timing
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IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS(1) SERIAL STREAM TIMING
Symbol tTAZ tTZA tOED tXCD tRSZ tZRS tZDO tRPW Characteristics TX0-7 Delay - Active to High Z TX0-7 Delay - High Z to Active Output Driver Enable Delay CCO Output Delay Reset to High Z High Z to Reset High Z to Valid Data Reset Pulse Width Min. 0 5 0 100 Typ.(2) 30 45 45 40 30 32 Max. 45 60 60 60 Unit ns ns ns ns ns ns cycles ns C4i cycles RL = 1K(3), CL = 150pF Test Conditions RL = 1K(3), CL = 150pF CL = 150pF RL = 1K(3), CL = 150pF CL = 150pF
NOTE: 1. Timing is over recommended temperature and power supply voltages. 2. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. 3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
ODE
Bit Cell Boundary
tOED
(GCI)
tOED
C4i (ST-BUS )
TX0-7
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tTAZ
Figure 10. Output Driver Enable
TX0-7
tTZA
TX0-7
RS tRPW TX
tXCD
CCO
tZDO tRSZ
5707 drw12
5707 drw14
tZRS
Figure 9. Serial Outputs and External Control
12
Figure 11. Reset
IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
AC ELECTRICAL CHARACTERISTICS(1) MICROPROCESSOR TIMING
Symbol tCSS tRWS tADS tCSH tRWH tADH tDDR tDHR tDSW tSWD tDHW tAKD Characteristics CS Setup from DS Rising R/W Setup from DS Rising Add Setup from DS Rising CS Hold after DS Falling R/W Hold after DS Falling Add Hold after DS Falling Data Setup from DTA Low on Read Data Hold on Read Data Setup on Write (Fast Write) Valid Data Delay on Write (Slow Write) Data Hold on Write Acknowledgment Delay: Reading Data Memory Reading/Writing Connection Memory Writing to Control Register Reading to Control Register Acknowledgment Hold Time Min. 0 5 5 0 5 5 10 10 10 5 10 Typ.(2) 50 560 300/370 45 45 20 Max. 90 122 1220 730/800 70 70 40 Unit ns ns ns ns ns ns ns ns ns ns ns CL = 150pF ns ns ns ns ns RL = 1K(3), CL = 150pF CL = 150pF RL = 1K(3), CL = 150pF Test Conditions
tAKH
NOTE: 1. Timing is over recommended temperature and power supply voltages. 2. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. 3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
DS
CS
tCSS
tCSH
tRWS R/W
tRWH
tADS A0-A5
tADH
D0-D7 READ tSWD tDSW D0-D7 WRITE tDDR tAKD
VALID DATA
tDHR
VALID DATA
tDHW tAKH
DTA
5707 drw15
Figure 12. Motorola Non-Multiplexed Bus Timing
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ORDERING INFORMATION
IDT XXXXXX Device Type XX Package X Process/ Temperature Range BLANK Commercial (-40C to +85C)
J PV DB
Plastic Leaded Chip Carrier (PLCC, J44-1) Small Shrink Outline Package (SSOP, SO48-1) Plastic Quad Flatpack (PQFP, DB44-1)
72V8985
256 x 256 3.3V Time Slot Interchange Digital Switch
5707 drw15
DATASHEET DOCUMENT HISTORY
05/24/2000 08/21/2000 01/24/2001 04/05/2001 03/10/2003 05/09/2003 08/20/2003 pgs. pgs. pgs. pg. pg. pgs. pg. 1, 2, 13 and 14. 1, 2 and 14. 1 and 9. 11. 13. 1, 2, and 14. 9. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
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for Tech Support: 408-330-1753 email: TELECOMhelp@idt.com

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